This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
A problem facing memory devices, for example, DRAM, is that the operational bandwidth may be more influenced by its configuration rather than just the peak bandwidth. The peak bandwidth rapidly increases between DRAM generations. For example, the LPDDR2 x32 200 MHz generation had a peak bandwidth of approximately 1600 MB/s, while the later LPDDR2 x32 400 MHz generation had a peak bandwidth of approximately 3200 MB/s.
With a bad bank allocation, the performance of a memory device can be very poor. When every access operation hits a different row in the same bank, a bad row hit ratio is experienced. For example, with LPDDR3 x32 800 MHz, this situation may give only 6% of the peak bandwidth. Typically, the memory bandwidth is expected to be 70% of the peak bandwidth. Thus, much less performance than expected is attained with bad memory space allocation.
Such problems may occur when using an open page policy such as commonly used in mobile systems. An open page policy leaves a page (e.g., a DRAM row) open after an access operation so that future accesses to the same page do not need to wait for the row to get re-opened. As a corollary, adding faster memories (and/or newer memories) does not improve the performance for such bank accesses. That is, newer and higher rated memories provide relatively less benefit.
Typically, the main memory is reserved by an operating system (OS). With current operating systems, the memory is reserved mainly from subsequent locations in order to keep the allocated memory space continuous. This has the effect that the memory bank usage balancing (and thus memory performance) depends mainly on the address mapping used. Some commonly used mappings are Bank-Row-Column (BRC) and Row-Bank-Column (RBC).
Contemporary memory systems may try to solve the problems encountered with bad allocations by usage of cache memories. More data than wanted is accessed from the main memory to a cache memory. It is hoped, that that excess data is needed in future accesses. However, if that data is not needed, it only consumes extra power, takes DRAM processing time and consumes cache memory (with the useless data in the cache).
Another way used to try to solve these problems is to increase the total amount of banks. Today, DRAM's may have 2, 4 or 8 banks per die, but other devices, like ones based on recent DRAM standards or Rambus XDR DRAM, may have 16 or 32 banks. In multi-channel memories, the total number of banks may be increased, but the number of banks per channel stays the same or even decreases. However, as mentioned above, increasing the number of banks does not improve the worst case scenarios.
Other techniques to solve the problem include trying to detect abnormal memory functionality in order to correct the memory operation before a system crash; however, a bad memory allocation is not considered an abnormal memory functionality.
A DRAM memory controller may be introduced which includes a page-tracking buffer (PTB). The PTB keeps track of open pages in the memory system. Unfortunately, this open page does not address the issue where bad memory allocation causes unacceptable performance.
Data elements may be interleaved across different banks Those data element can then be accessed in parallel from several banks. SRAM memory may allow parallel accesses. However, this does not improve DRAM memory bandwidth.
What is needed is a way to optimize memory bank bandwidth using memory bank based allocations.